1. Field of the Invention
The present invention relates to a delay calculating method in a semiconductor integrated circuit and a cell characterizing method used in the delay calculation.
2. Description of the Related Art
In a final state of designing LSI, a delay calculation is processed for timing verification. In the delay calculation, a delay information of a cell used in a design data, a capacitance and a resistance value parasitizing a wiring, and a connection information of the cell are inputted in order to calculate how much delay value is generated in respective instances (logic element, logic gate, circuit block and the like) and wiring. The timing verification is performed based on a result of the delay calculation and design restrictions.
The delay calculation requires a delay library in which the delay information of the cell and an input pin capacitance value are registered. In the generation of the library for the delay calculation (extraction of a characteristic of the cell), the input pin capacitance value of the cell is extracted and registered in the delay library to be used in the delay calculation.
The value of the input pin capacitance is generally registered in the delay library as a value having a width such as one value or a maximum value and a minimum value as shown in, for example, the Library compiler User Guide or Prime Time User Guide (Synopsys Inc), which is hereinafter referred to as a conventional technology 1.
A method of calculating the input pin capacitance when the delay is calculated by obtaining one representative value of the input pin capacitance value and multiplying the one representative value by a coefficient dependent on an input slew (slew: how round a signal pulse is) was proposed, an example of which is recited in No. WO99/22320 of the PCT Publication. The method is hereinafter referred to as a conventional technology 2.
According to a conventional method of obtaining the input pin capacitance value registered in the library or the like and used, an average value of values obtained as a result of dividing an integrated value of a value of a current running into the input pin capacitance by a voltage value is registered in the library as the input pin capacitance as shown in the Signal Storm Manual (Cadence Inc.) when a delay time of the cell and a slew value in an output terminal are measured. The method is hereinafter referred to as a conventional technology 3.
However, the conventional methods have the following problems. In the conventional technology 1, the input pin capacitance is represented by one value, however, the input pin capacitance is actually different depending on an input transition with respect to the cell and a drive load capacitance. Therefore, the input pin capacitance value may be largely different to the value registered in the library depending on a status of the circuit (dimension of the input transition with respect to the cell and drive load capacitance)
Further, when the input pin capacitance having such a width as the maximum value and the minimum value is described in the conventional technology 1, it is possible to make an allowance for an amplitude of the input pin capacitance, which can include a worst value in the delay calculation. However, according to the foregoing method, the input pin capacitance can only be estimated to be relatively larger or smaller, which results in demanding an excessive margin. Therefore, the method may consequently reduce the number of obtained chips.
In the conventional technology 2, based on the understanding that the input pin capacitance is a value dependent on the input slew, a coefficient is calculated from a coefficient table provided with the input slew as an index for the input pin capacitance used as a basis, and the input pin capacitance as the basis is multiplied by the calculated coefficient so that the input pin capacitance is obtained when the delay is calculated. However, it is already known that the input pin capacitance really depends on not only the input slew but also the drive load capacitance, and the foregoing method fails to include the dependence of the input pin capacitance on the drive load capacitance. Further, the coefficient value by which the input pin capacitance value as the basis is multiplied may undergo an error because the coefficient is obtained through interpolation.
In the conventional technology 2, the error resulting from the interpolation in the input pin capacitance can be lessened when the number of points of the input slew is increased. However, the coefficient (the number of the points of the input slew) is generally obtained simultaneously when the delay value is characterized. Therefore, it is not practical to immoderately increase the coefficient. As a result, it is not possible to avoid the error generation in the coefficient by which the input pin capacitance is multiplied in the conventional technology.
Further, in the conventional technology 2, when the input pin capacitance value is obtained from the integrated value of the current running into the input capacitance value before a voltage of the input terminal shifts to a power-supply voltage or a voltage value 0 at the time of the characterization in the conventional manner, a value larger than the input pin capacitance in an actual circuit is extracted. This results in the generation of deviation in the delay calculation.
In the delay calculation, the input terminal of the cell and coupling capacitance in the cell continue to increase as a manufacturing process is increasingly finer and more precise. Because of the ongoing trend, there is such a recent problem that a delay calculation result at the cell level (gate level) does not coincide with a simulation obtained by a circuit simulator such as SPICE due to a distortion generated in a signal waveform.